Tunable three dimensional inductor

ABSTRACT

A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.13/964,539, filed Aug. 12, 2013, which is incorporated by referenceherein in its entirety.

BACKGROUND

Inductors are passive electrical components that are configured togenerate a magnetic field that stores energy. Inductors are used in awide variety of integrated circuit (IC) applications, such as, forexample, voltage regulators and many radio frequency (RF) circuits. Atleast some known inductors can be built directly on integrated circuitsusing existing integrated chip fabrication processes.

When designing the inductor, it is important to consider the inductancevalue as well as the quality factor (Q) and occupation area of theinductor. The inductance of an integrated inductor is a measure of theamount of energy stored in an inductor. The Q factor is a ratio of theamount of energy stored in an inductor to the amount of energydissipated in the inductor, and is a measure of its efficiency. An idealinductor has a relatively high Q factor. The higher the Q factor of theinductor, the closer it approaches the behavior of an ideal, lossless,inductor.

BRIEF DESCRIPTION OF THE FIGURES

FIGS. 1A-D show a schematic view, an isometric view, a front view, and aside view of an example of a tunable 3D inductor, respectively inaccordance with some embodiments.

FIG. 2A illustrates an schematic view of the tunable 3D inductor whereheight h of the wires of the inductor is tunable in accordance with someembodiments.

FIG. 2B depicts the relationship between height of the tunable wires andthe inductance value of a tunable 3D inductor in accordance with someembodiments.

FIG. 3A illustrates a schematic view of a tunable 3D inductor wherepitch p of each wire of the inductor is tunable in accordance with someembodiments.

FIG. 3B depicts the relationship between the number of wires which pitchp has been adjusted and the inductance value of the tunable 3D inductor,in accordance with some embodiments.

FIGS. 3C-3F show isometric views of the tunable 3D inductor with 0, 1,2, and 3 wires having pitches tuned, respectively, in accordance withsome embodiments.

FIG. 4A illustrates a schematic view of a tunable 3D inductor where thenumber of wires of the inductor is tunable in accordance with someembodiments.

FIG. 4B depicts the relationship between the number of wires 102 and theinductance value of the tunable 3D inductor in accordance with someembodiments.

FIGS. 4C-4F show isometric views of the tunable 3D inductor having 3, 4,5, and 6 number of wires (or turns), respectively in accordance withsome embodiments.

FIGS. 5A-B show isometric views of a tunable 3D inductor before andafter the hybrid tuning approach has been applied to the 3D inductor,respectively in accordance with some embodiments.

FIGS. 6A-6H show an example of a manufacturing process of a packagehaving two chips and the tunable 3D inductor with tunable wires packagedtogether in accordance with some embodiments.

FIGS. 7A-7H show an example of a manufacturing process of a packagehaving two chips and the tunable 3D inductor with tunable wires packagedtogether in accordance with some embodiments.

FIGS. 8A-8F show another example of a manufacturing process of a packagehaving one chip and the tunable 3D inductor with tunable wires packagedtogether in accordance with some embodiments.

FIGS. 9A-9F show another example of a manufacturing process of a packagehaving one chip and the tunable 3D inductor with tunable wires packagedtogether in accordance with some embodiments.

FIGS. 10A-10G show another example of a manufacturing process of apackage having one chip and the tunable 3D inductor with tunable wirespackaged together in accordance with some embodiments.

FIG. 11 is a flow chart of a method for forming a tunable 3D inductorwherein one or more of height, pitch, and number of turns of the wiresof the tunable 3D inductor are tuned to adjust the inductance value andQ factor of the 3D inductor in accordance with some embodiments.

DETAILED DESCRIPTION

In the description, relative terms such as “lower,” “upper,”“horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and“bottom” as well as derivative thereof (e.g., “horizontally,”“downwardly,” “upwardly,” etc.) should be construed to refer to theorientation as then described or as shown in the drawing underdiscussion. These relative terms are for convenience of description anddo not require that the apparatus, assembly, and/or system beconstructed or operated in a particular orientation. Terms concerningattachments, coupling and the like, such as “connected” and“interconnected,” refer to a relationship wherein structures are securedor attached to one another either directly or indirectly throughintervening structures, as well as both movable or rigid attachments orrelationships, unless expressly described otherwise,

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. The drawings are not drawn toscale. In the various drawings, like reference numerals indicate likeitems, unless expressly indicated otherwise in the text.

Conventional two-dimensional (2D) and three-dimensional (3D) inductorsare fabricated using pre-designed masks to form a redistribution layer(RDL) of interconnects and via connections of the inductors, where theredistribution layer is an extra metal layer on an IC chip that can beused to connects the vias of the inductors. Since they are made usingpre-designed masks that are not adjustable during the manufacturingprocess, the inductance values of the conventional inductors are fixedand not fine tunable or changeable during the manufacturing process.

The inventors have discovered embodiments and methods for a tunablethree-dimensional (3D) inductor that can be packaged with one or morechips in an on-chip package, wherein the configuration and inductancevalue of the 3D inductor are adjustable during the manufacturing processof the inductor. Specifically, the tunable 3D inductor includes aplurality of tunable wires, vias, and metal interconnects in athree-dimensional structure in the same package of one or more IC chipsto which the inductor connects. In some embodiments, the inductancevalue of the 3D inductor is tuned by adjusting one or more of heights,pitches, and turns of wires of the inductor. By tuning various physicalparameters and the extra space provided by the three-dimensionalconfiguration, the 3D inductor achieves an adjustable (increased)inductance value and high Q factor with small occupation area on thepackage with the chips.

FTG. 1A shows a schematic view of an example of tunable 3D inductor 100.FIGs. 1B, 1C, and 1D show an isometric view, front view, and side viewof the 3D tunable inductor 100 in FIG. 1A, respectively. As shown inFIGS. 1A-D, tunable 3D inductor 100 includes a plurality of tunablewires 102, each of which connects on one end to a pair of a plurality ofvias 104 arranged with certain spacing among them. The plurality of vias104 are connected to each other at another end through interconnects 106in a metal layer (e.g., a redistribution layer (RDL), which is an extrametal layer on an IC chip, carrier, interposer or fan-out wafer that canbe used to connect the vias of the inductors) to form a functional 3Dinductor 100. In some embodiments, wires 102, vias 104, andinterconnects 106 are made of conductive materials. In some embodiments,wires 102 and vias 104 are made of thick metal in order to reduce lossand increase Q factor for the 3D inductor. In some embodiments, thephysical configuration of the tunable 3D inductor 100 is characterizedat least by three parameters—height h of wire 102 as measured by thedistance from the top of wire 102 to contact point with via 104, pitch pas measured by the distance along the horizontal or vertical directionbetween a pair of adjacent or non-adjacent vias 104 connected by thesame wire 102, and number of turns t of wires 102 or simply the numberof wires 102—in tunable 3D inductor 100. In some embodiments, thephysical configuration of 3D inductor 100 is adjusted by independentlytuning each of the three parameters of 3D inductor 100, height h, pitchp, and number of wire turns t as discussed in details below, and anyadjustment to one of these parameters will affect the inductance valueand Q factor of 3D inductor 100.

FIG. 2A illustrates a schematic view of tunable 3D inductor 100 whereheight h of wires 102 is tunable, e.g., the height of wires 102 isadjustable to tune the inductance value of 3D inductor 100. As shown bythe diagram of FIG. 2B depicting the relationship between height h oftunable wires 102 and the inductance value of tunable 3D inductor 100,the inductance value of 3D inductor 100 increases as the height oftunable wires 102 increases. As shown in FIG. 2B, the inductance valueof 3D inductor 100 increases from 3 nH to 5 nH as the height of tunablewires 102 increases from 100 μm to 400 μm. Based on the correlation, theinductance value of 3D inductor 100 is increased by tuning andincreasing the height of tunable wires 102 of 3D inductor 100. Since theQ factor of an inductor is proportional to its inductance value, theincreased inductance value of 3D inductor 100 as a result of theincreased height of wires 102 also leads to an increase in the Q factorof 3D inductor 100.

FIG. 3A illustrates an schematic view of tunable 3D inductor 100 wherepitch p of each wire 102 is tunable, e.g., the distance along thehorizontal or vertical direction between the two connection points ofeach wire 102 to vias 104 is adjustable to tune the inductance value of3D inductor 100. In some embodiments, tuning or adjusting the pitch ofwire 102 means moving at least one connection point of wire 102 from onevia 104 to another so that the distance between the two via connectionpoints of wire 102 changes (increases). FIG. 3B depicts the relationshipbetween the number of wires 102 which pitch p has been adjusted(increased) and the inductance value of tunable 3D inductor 100. FIGS.3C-3F show isometric views of tunable 3D inductor 100 with 0, 1, 2, and3 wires 102 having pitches tuned/increased, respectively. As shown inFIG. 3B-3F, the inductance value of 3D inductor 100 increases as thenumber of wires 102 with adjusted pitches increases. In the example ofFIG. 3B, the inductance value of 3D inductor 100 increases from 4 nH to6 nH as the number of wires 102 with adjusted pitches increases from 0to 3. Based on the correlation, the inductance value (as well as the Qfactor) of 3D inductor 100 is increased by tuning/increasing the pitchesfor one or more of the plurality of tunable wires 102 of 3D inductor100.

FIG. 4A illustrates a schematic view of tunable 3D inductor 100 wherethe number of turns t, or simply the number of wires 102 is tunable,e.g., the number of wires 102 is adjustable (increased or decreased) totune the inductance value of 3D inductor 100. FIG. 4B depicts therelationship between the number of wires 102 and the inductance value oftunable 3D inductor 100. FIGs, 4C-4F show isometric views of tunable 3Dinductor 100 having 3, 4, 5, and 6 number of wires 102 (or turns),respectively. As shown in FIG. 4B, the inductance value of 3D inductor100 increases as the number of wires 102 increases. In the example ofFIG. 4B, the inductance value of 3D inductor 100 increases from lessthan 4 nH to over 7 nH as the number of wires 102 increases from 3 to 6.Based on the correlation, the inductance value (as well as the Q factor)of 3D inductor 100 is increased by tuning/increasing the number of wires102 of 3D inductor 100.

In some embodiments, wires 102 of tunable 3D inductor 100 are adjustedusing a hybrid tuning approach, which utilizes more than one of the wiretuning methods described above. For example, in some embodiments, ahybrid tuning approach tunes one or more of the height h, pitch p, andturns t of wires 102 of the inductor. FIG. 5A-B show isometric views oftunable 3D inductor 100 before and after the hybrid tuning approach hasbeen applied to 3D inductor 100, respectively. In the example of FIG.5B, both the pitches as well as the number (or turns) of wires 102 areadjusted in order to increase the inductance value as well as Q factorof 3D inductor 100.

In some embodiments, the manufacturing process of a package thatincludes both one or more chips and tunable 3D inductor 100 is dividedinto two stages—the preformed stage, during which the fixed or untunableportion of the 3D inductor is formed, and the fine tuning stage, duringwhich the tunable portion of the 3D inductor is formed. FIGS. 6A-6H showan example of a manufacturing process of package 600 having two chipsand a tunable 3D inductor with tunable wires packaged together. Moreparticularly, FIGS. 6A-6D illustrate the manufacturing steps during thepreformed stage, and FIGS. 6E-6H illustrate the manufacturing stepsduring the fine tuning stage. As shown in FIG. 6A, a bottomredistribution layer 604 of metal interconnections is formed on top ofcarrier 602. A bottom chip 606 is placed on top of the bottomredistribution layer 604 as shown in FIG. 6B. In some embodiments, thebottom chip 606 is sealed within molding compound (MC) 608 and aplurality of through assembly vias (TAV)610 (104 of inductor 100) areformed within MC 608 and connected with each other via—redistributionlayer 604 as shown in FIG. 6C. A top redistribution layer 612 is formedon the top surface of MC 608 as shown in FIG. 6D. As shown in FIG. 6E,top chip 614 is placed (for example, via bumping) on top of topredistribution layer 612. Wires 616 (102 of inductor 100) of 3D inductor100 are connected to TAVs 610 to form the inductor and are fine-tunedusing one or more of the methods discussed above to adjust theinductance value of inductor 100 as shown in FIG. 6F. Once 3D inductor100 is formed and tuned, both wires 616 and top chip 614 are sealedwithin top MC 618 to form package 600 as shown in FIG. 6G. Balls 620 aremounted on the bottom of package 600 as shown in FIG. 6H.

FIGS. 7A-7H show an example of a manufacturing process of package 700having two chips and a tunable 3D inductor with tunable wires packagedtogether. As shown in FIG. 7A, a bottom redistribution layer 704 ofmetal interconnections is formed on top of carrier 702. A bottom chip706 is placed on top of the bottom redistribution layer 704 as shown inFIG. 7B. In some embodiments, the bottom chip 606 is sealed withinmolding compound (MC) 708 and a plurality of through assembly vias (TAV)710 (104 of inductor 100) are formed within MC 708 and connected witheach other via redistribution layer 704 as shown in FIG. 7C. A topredistribution layer 712 is formed on the top surface of MC 708 as shownin FIG. 7D. As shown in FIG. 7E, top chip 714 is placed (for example,via bumping) on top of top redistribution layer 712. As shown in FIG.7F, top chip 714 is sealed in top MC 716, which has its heightcontrolled so that vias 718 extended from TAVs 710 and grown within topMC 716 are controlled to a desired height. Once vias 718 are formed intop MC 716 with the controlled height, a final redistribution layer 720is formed on top of top MC 716 where final redistribution layer 720includes wires 722 that serve as wires 102 to connect vias 718 to form3D inductor 100. In some embodiments, the height of vias 718 plus theheight of TAV 710 determines the height of wires 722 (102 of inductor100) in final redistribution layer 720. Consequently, in someembodiments, the height of wires 722 and thus the inductance value of 3Dinductor 100 are tuned by controlling the height of top MC 716 duringthe fine tuning stage of the manufacturing process. Finally, balls 724are mounted on the bottom of package 700 as shown in FIG. 7H similar toFIG. 6H.

FIGS. 8A-8F show an example of a manufacturing process of package 800having one chip and a tunable 3D inductor with tunable wires packagedtogether. Package 800 is formed on substrate 802, which can be glass,organic, or silicon material, and through substrate vias (TSVs) 804 areformed in substrate 802 as shown in FIG. 8A. An redistribution layer 806is formed on top of substrate 802 to connect TSVs 804 together as shownin FIG. 8B, and chip 808 is placed (e.g., via bumping) on top ofredistribution layer 806 as shown in FIG. 8C. Chip 808 is sealed withinmolding compound (MC) 810 as shown in FIG. 8D. Wires 812 (102 ofinductor 100) are connected to TSVs 804 at the bottom of the viasinstead at the top of these vias to form inductor 100 as shown in FIG.8E. In some embodiments, wires 812 are fine-tuned using one or more ofthe methods discussed above to adjust the inductance value of inductor100. Once 3D inductor 100 is formed and tuned, wires 812 are sealedwithin liquid molding compound (LMC) 814 at the bottom of glasssubstrate 802 with balls 816 mounted on the bottom to form package 800as shown in FIG. 8F.

FIGS. 9A-9F show an example of a manufacturing process of package 900having one chip and a tunable 3D inductor with tunable wires packagedtogether. Package 900 is formed on substrate 902, which can be glass,organic, or silicon material, and vias 904 are formed in substrate 902as shown in FIG. 9A. A bottom redistribution layer 906 and a topredistribution layer 908 are formed on the bottom and the top ofsubstrate 902 to connect vias 904 together as shown in FIG. 9B and 9C,respectively. As shown in FIG. 9D, chip 910 is placed (e.g., viabumping) on top of redistribution layer 908, and wires 912 (102 ofinductor 100) are connected to vias 904 at the top of these vias to formthe 3D inductor. In some embodiments, wires 912 are fine-tuned by one ormore of the methods discussed above to adjust the inductance value ofinductor 100. Chip 910 and the tuned wires 912 are then sealed withinmolding compound (MC) 914 as shown in FIG. 9E. Balls 916 are mounted onthe bottom of bottom redistribution layer 906 to form package 900 asshown in FIG. 9F.

FIGS. 10A-10F show an example of a manufacturing process of package 1000having one chip and tunable 3D inductor with tunable wires packagedtogether. Package 1000 is formed on substrate 1002, which can be glass,organic, or silicon material, and vias 1004 are formed in substrate 1002as shown in FIG. 10A. A bottom redistribution layer 1006 and a topredistribution layer 1008 are farmed on the bottom and the top ofsubstrate 1002 to connect vias 1004 together as shown in FIG. 10B and10C, respectively. As shown in FIG. 10D, chip 1010 is placed (e.g., viabumping) on top of redistribution layer 1008. As shown in FIG. 10E, chip1010 is sealed in MC 1012, which has its height controlled so that vias1014 extended from vias 1004 and grown within MC 1012 are controlled toa desired height. Once vias 1014 are formed in MC 1012 with thecontrolled height, a final redistribution layer 1016 is formed on top ofMC 1012 where final redistribution layer 1016 includes wires 1018 thatserve as wires 102 as described above with respect to FIGS. 1A-5B toconnect vias 1014 to form the 3D inductor. In some embodiments, theheight of vias 1014 plus the height of vias 1004 determines the heightof wires 1018 (102 of inductor 100) in final redistribution layer 1016.Consequently, the height of wires 1018 and thus the inductance value of3D inductor 100 are tuned by controlling the height of MC 1012 duringthe fine tuning stage of the manufacturing process. Finally, balls 1020are mounted on the bottom of package 1000 as shown in FIG. 10G.

FIG. 11 is a flow chart 1100 of one example of a method for forming atunable 3D inductor wherein one or more of height, pitch, and number ofthe wires of the tunable 3D inductor are tuned to adjust the inductancevalue and Q factor of the 3D inductor.

At step 1102, a plurality of vias are formed in a substrate or a moldingcompound, wherein the vias are arranged with certain spacing among them.

At step 1104, an metal layer is formed wherein the interconnects of themetal layer connects the plurality of vias on one end.

At step 1106, a plurality of tunable wires are formed to connect theplurality of vias on the other end to form a 3D inductor.

At step 1108, the tunable wires are tuned to adjust the physicalconfigurations and inductance value of the 3D inductor.

At step 1110, the 3D inductor is sealed together with one or more chipsto form an integrated package.

In some embodiments, a method comprises forming a plurality of vias in asubstrate or a molding compound, wherein the vias are arranged withspacing among them. The method further comprises forming a metal layerwherein the interconnects of the metal layer connects the plurality ofvias on one end of the vias and forming a plurality of wires to connectthe plurality of vias on the other end of the vias to form athree-dimensional (3D) inductor. The method also comprises tuning one ormore of the plurality wires to adjust the physical configurations andinductance value of the 3D inductor.

In some embodiments, the method further comprises sealing the 3Dinductor together with one or more chips to form an integrated package.

In some embodiments, the method further comprises forming the pluralityof tunable wires and the plurality of vias with metal.

In some embodiments, the method further comprises forming the metallayer as a redistribution layer (RDL) of interconnects.

In some embodiments, the method further comprises tuning height of theplurality of tunable wires to adjust the inductance of the 3D inductor,wherein the inductance of the 3D inductor increases when the height ofthe plurality of tunable wires increases.

In some embodiments, the method further comprises tuning pitch of one ormore of the plurality of tunable wires to adjust the inductance of the3D inductor, wherein the inductance of the 3D inductor increases whenthe number of tunable wires which pitches are tuned increases.

In some embodiments, the method further comprises tuning number or turnsof the plurality of tunable wires to adjust the inductance of the 3Dinductor, wherein the inductance of the 3D inductor increases when thenumber or turns of tunable wires increase.

In some embodiments, the method further comprises forming the package intwo stages by forming the fixed or untunable portion of the 3D inductorduring a preformed stage, and forming the tunable portion of the 3Dinductor during a fine tuning stage.

In some embodiments, the method further comprises forming the pluralityof vias in a molding compound.

In some embodiments, the method further comprises forming the pluralityof vias in a substrate.

In some embodiments, the method further comprises forming the pluralityof vias partly in a substrate and partly in a molding compound.

In some embodiments, a method comprises forming a plurality of vias in asubstrate or a molding compound, wherein the vias are arranged withspacing among them. The method further comprises forming a metal layerwherein the interconnects of the metal layer connects the plurality ofvias on one end of the vias and forming a plurality of wires to connectthe plurality of vias on the other end of the vias to form athree-dimensional (3D) inductor. The method also comprises tuning atleast two of height, pitches, and number of turns of one or more of theplurality wires to adjust the physical configurations and inductancevalue of the 3D inductor.

In some embodiments, a tunable three-dimensional (3D) inductor comprisesa plurality of vias arranged with at least one spacing among them, aplurality of interconnects in a redistribution layer (RDL), wherein theplurality of interconnects connect to respective ones of the pluralityof vias on one end of the vias, and a plurality of wires that connect tothe plurality of vias on the other end of the vias to form the 3Dinductor, wherein an inductance value of the 3D inductor is based on atleast one of a height, pitch, and turn of the plurality of wires.

In some embodiments, the plurality of tunable wires and the plurality ofvias are made of metal.

In some embodiments, height of the plurality of wires is tuned to adjustthe inductance of the 3D inductor, wherein the inductance of the 3Dinductor increases when the height of the plurality of tunable wiresincreases.

In some embodiments, pitch of one or more of the plurality of tunablewires is tuned to adjust the inductance of the 3D inductor, wherein theinductance of the 3D inductor increases when the number of tunable wireswhich pitches are tuned increases.

In some embodiments, number or turns of the plurality of tunable wiresis tuned to adjust the inductance of the 3D inductor, wherein theinductance of the 3D inductor increases when the number or turns oftunable wires increase.

In some embodiments, the plurality of vias are formed in a moldingcompound.

In some embodiments, the plurality of vias are formed in a substrate.

In some embodiments, the plurality of vias are formed partly in amolding compound and partly in a substrate.

Although the invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly, to include other variants and embodimentsof the invention, which may be made by those skilled in the art withoutdeparting from the scope and range of equivalents of the invention.

What is claimed is:
 1. A three-dimensional (3D) inductor, comprising: anarray of vias in a first layer; a plurality of interconnects in a secondlayer, wherein the plurality of interconnects connect the array of viason one end of the array of vias; and a plurality of wires that connect asubset of the array of vias on the other end of the array of vias so asto form the 3D inductor, wherein each of the plurality of wiresprotrudes away from a top surface of the first layer with a spacingdisposed between each of the plurality of wires and the top surface ofthe first layer, and wherein an inductance value of the 3D inductor isbased on at least one of a height of the plurality of wires, turns ofthe plurality of wires, and a pitch of the array of vias.
 2. The 3Dinductor of claim 1, wherein: the plurality of wires and the array ofvias are each made of metal.
 3. The 3D inductor of claim 1, wherein: theinductance value of the 3D inductor increases when the height of theplurality of wires increases.
 4. The 3D inductor of claim 1, wherein:the inductance value of the 3D inductor increases when the pitch of thearray of vias increases.
 5. The 3D inductor of claim 1, wherein: theinductance value of the 3D inductor increases when the turns of theplurality of wires increase.
 6. The 3D inductor of claim 1, wherein: thefirst layer comprises a molding compound.
 7. The 3D inductor of claim 1,wherein: the first layer comprises a substrate.
 8. The 3D inductor ofclaim 1, wherein: the first layer comprises a molding compound and asubstrate.
 9. A three-dimensional (3D) inductor, comprising: a pluralityof vias extending through a first layer; a plurality of interconnectsdisposed over a second layer, wherein the plurality of interconnectsconnect the plurality of vias in the first layer on one end of the vias;and a plurality of wires that connect the plurality of vias on the otherend of the vias to form the 3D inductor, wherein each of the pluralityof wires protrudes away from a surface of the first layer to cause eachof the plurality of wires to have at least a portion to be laterallyspaced apart from the surface of the first layer, and wherein aninductance value of the 3D inductor is determined based on at least oneof a height of the plurality of wires, turns of the plurality of wires,and a pitch of the plurality of vias.
 10. The 3D inductor of claim 9,wherein: the plurality of wires and the plurality of vias are made ofmetal.
 11. The 3D inductor of claim 9, wherein: the inductance value ofthe 3D inductor increases when the height of the plurality of wiresincreases.
 12. The 3D inductor of claim 9, wherein: the inductance valueof the 3D inductor increases when the pitch of the plurality of viasincreases.
 13. The 3D inductor of claim 9, wherein: the inductance valueof the 3D inductor increases when the turns of the plurality of wiresincrease.
 14. The 3D inductor of claim 9, wherein: the first layer isdisposed either above or below the second layer.
 15. The 3D inductor ofclaim 9, wherein: the plurality of wires are embedded in a moldingcompound.
 16. The 3D inductor of claim 1, wherein: the first layercomprises a molding compound and/or a substrate.
 17. A three-dimensional(3D) inductor, comprising: a plurality of vias extending through asubstrate or a molding compound; a plurality of interconnects connectthe plurality of vias on one end of the vias; a plurality of wires thatconnect the plurality of vias on the other end of the vias to form the3D inductor, wherein each of the plurality of wires protrudes away froma surface of the substrate or the molding compound with a spacingdisposed between each of the plurality of wires and the surface of thesubstrate or the molding compound, and wherein an inductance value ofthe 3D inductor is determined based on at least one of a height of theplurality of wires that corresponds to a distance from a top of each ofthe plurality of wires to the surface of the substrate or the moldingcompound, a pitch that corresponds to a distance between a pair of theplurality of vias, and a number of the plurality of wires.
 18. The 3Dinductor of claim 9, wherein: the inductance value of the 3D inductorincreases when the height of the plurality of wires increases.
 19. The3D inductor of claim 9, wherein: the inductance value of the 3D inductorincreases when the pitch increases.
 20. The 3D inductor of claim 9,wherein: the inductance value of the 3D inductor increases when thenumber of the plurality of wires increases.